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L6660
MILLI-ACTUATOR DRIVER
PRODUCT PREVIEW
90V BCD MIXED TECHNOLOGY SO24 PLASTIC SMD PACKAGE 4.5 TO 13.2V OPERATIVE VOLTAGE 25 TO 35V OUTPUT VOLTAGE RANGE SELECTABLE BY EXTERNAL RESISTORS FULL-WAVE RESONANT DC-DC CONVERTER USING SINGLE COIL FOR DUAL HIGH VOLTAGE GENERATOR WITH OUTPUT SLEW RATE CONTROL AND SELF CURRENT LIMITING FOR LOW EMI 35V OR 0/+70V OPERATIVE VOLTAGE DRIVING CONFIGURATION MODES: 1. SINGLE ENDED VOLTAGE MODE 2. DIFFERENTIAL VOLTAGE MODE 3. SINGLE ENDED CHARGE MODE DOUBLE OPERATIONAL AMPLIFIERS WITH 500KHZ GAIN BANDWIDTH PRODUCT AND LOAD DRIVING CAPABILITY FROM 0.4nF UP TO 24nF ANALOG VOLTAGE SHIFTING CIRCUITRY BLOCK AND APPLICATION DIAGRAM
SO24(Shrink)
INTERNAL 2.5V VOLTAGE REFERENCE POWER SAVING SLEEP MODE USER SPECIFIED INPUT REFERENCE (2.25V DC) DESCRIPTION The L6660 is a piezoelectric actuator driver.
[24] HVP
[7] SLEEP
SLEEP
-
HV P
1 K
[17] INB(i nv) [16] INB(not inv)
[18] OUTK-B
B
+
[19] OUT1-B
[10] Vosh [11] Vin0-5 Shifter Vosh=Vin-Vref
HVM HV P
1
1
K
[23] HVM
K
From DAC OUTPUT
[8] INA(i nv) [9] INA(not inv)
-
[6] OUTK-A
V51 2
A
+
[5] OUT1-A
HVM
[15] WENA
1
K
V5/12
[3] COIL
47H
2.2nF +35V
[ 4] AorB [1] AandB [20] V5/12AP [14] IN Vref
MUX Controll Logic
A-GND
Internal Current Bias
+
Back-Up Oscill.
DC-DC LOGIC
Rfdb1 220nF
Rs
D igital Pwr Supply [13] Vref out
-
68nF
HVM
Rfdb2
Internal Band-g ap an d 2.5 reference Voltage
-35V
:5
220nF
[ 12] GND-A [21] Vfdb [22] RCcomp [2] GND-P
100nF 47nF
HVP=VrefIN(1+Rfdb1/Rfdb2)
March 2000
This is preliminary information on a new product now in development. Details are subject to change without notice.
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L6660
PIN CONNECTION SO24-SHIRINK (Top view)
A and B GND-P COIL A or B. OUT1-A OUTK-A SLEEP INA(inv) INA(not inv) VOSH Vin 0-5 GND-A
1 2 3 4 5 6 7 8 9 10 11 12
PINCON
24 23 22 21 20 19 18 17 16 15 14 13
HVP HVM RC comp VFDB V5/12-AP OUT1-B OUTK-B INB(inv) INB(not inv) WENA Vref IN Vref OUT
PIN FUNCTIONS
N. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name AandB GND-P COIL AorB OUT1-A OUTK-A SLEEP INA (inv) INA (not inv) Vosh Vin 0-5 GND-A Vref OUT Vref IN WENA INB (not inv) INB (inv) OUTK-B OUT1-B V5/12-AP Vfdb RC comp HVM HVP MUX Enable (see Tab. 1). Power ground. Coil for positive step UP and capacitor for negative charge. MUX command Aor B input selection (0 = A; 1 = B). Output ampl.A. Hi current output ampl.A. Sleep mode for stand-by condition (0=SLEEP 1=operative). Inverting input of A-amplifier. Non Inverting input of A-amplifier. Analog level shifter output Vin-Vref (-2.5 to +2.5 dynamic range) Analog level shifter input positive voltage. Analog ground. Precise 2.5V reference voltage. Input for external reference voltage. Multiplexer Enable, Falling Edge sensitive. Non Inverting input of B-amplifier. Inverting input of B-amplifier. Hi current output ampl.B. Output ampl.B. Analog&Power voltage supply 5 to 12V. Feedback voltage for HVP regulator. DC-DC converter compensation network. Negative High voltage generated op. amp. supply. Positive High voltage generated op. amp. supply. Description
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ABSOLUTE MAXIMUM RATINGS
Symbol V512 HVP HVM IN A&B Tamb Tstg Parameter Supply voltage pin 17 referred to Ground Positive high voltage referred to HVM Negative high voltage referred to Ground Amplifier input voltage common mode Operative Ambient Temperature Storage Temperature Value 14 75 -38 6 -20 to +80 -40 to +125 Unit V V V V C C
All the voltage value are referred to ground unless otherwise specified.
ELECTRICAL CHARACTERISTICS (All the following parameters are specified @ 27C and V5/12 = 12V, unless otherwise specified.)
Symbol V5/12 HVP (1) Parameter Main power supply Output positive Voltage Min. 4.5 Double Supply Voltage V 512 8 27 Double Supply Voltage V 512 < 8 25 27 Single Supply Voltage V512 8 Single Supply Voltage V512 < 8 25 -HVP-1 External filter cap. 100nF ILOAD = 0mA Test Condition Typ. 35 35 70 35 -HVP+1 0.8 Max. 13.2 Unit V V V V V V V
HVM HVripple I, hvp I, hvm Top Fswitch (2) Rds, on Iboost Vsup
Output negative voltage HVP, HVM ripple Characterized only, Not Tested Output current (see figure 1) Time to operating condition Switching Frequency Boost transistor ON resistance Boost transistor current limiting Minimum OpAmp supply Voltage (HVP if externally given) OpAmp DC gain OpAmp Gain Bandwidth product OpAmp Input dynamic voltage OpAmp Output dynamic voltage OpAmp Bias supply current (both) OpAmp Dynamic Output Average current with external supply OpAmp Positive power supply rejection ratio OpAmp Negative power supply rejection ratio OpAmp Load capacitance range OpAmp Integration capacitance OpAmp Current ratio OUTK/OUT1 OpAmp Ioutk
5 Refer to Block diagram page1/10 300 4 850 Double Supply Single Supply V512 +4 V512 +4 130 500 -5 1.2 HVM 5 5 HVP 9 +75
ms kHz mA V V dB KHz V V V mA mA
DC gain GBW DCinp Vout DC, Ibias Iout (3) PSRR,P PSRR,N Cload C int K Ierr
Cload 0.4nF to 24nF Double Supply Voltage Double supply Single supply Capacitive load |HVP| = |HVM| = 35V
-75
@ 50kHz not tested in production @ 50kHz not tested in production Voltage mode Gain min 20dB Charge mode Gain min 20dB 0.4 0.4 9.8 -100
-50 -50 24 24 10.2 +100
dB dB nF nF A
10
Iout1 = 0
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L6660
ELECTRICAL CHARACTERISTICS (continued)
Symbol Vout0 VrefOUT Ivref Vref, cap Vshifted Shifter Gain Parameter OpAmp Output Voltage with 0V Input Voltage Reference Voltage PIN13 Reference Voltage Output Current Filter capacitor at PIN13 Voltage shift value (VPIN11 - VPIN10) Analog Voltage Shifter DC Voltage Gain V10 V11 BWVshift VrefIN Isleep EAoff Shifter circuitry Band Width External reference voltage (PIN14) Total current in Sleep Mode DC-DC converter Error Amplifier Input voltage Offset (VPIN14-VPIN21) Error amplifier Current Capability Total HVP precision Voltage level for 0 logic at digital input pin (Pin 1-4-7-15) Voltage level for 1 logic at digital input pin (Pin 1-4-7-15) Decay period for V = |19V| Operative period from Not Selected phase to Selected phase for each driver Test Condition External feedback programmed for DC gain value <30V/V Min. -1 2.4 -1 10 VrefIN -1.5% 0.975 Typ. Max. +1 2.6 +1 100 VrefIN +1.5% 1.025 Unit V V mA nF V
2.5
1.0V Vin0-5 3.5V VPIN11 = VREFIN V'10 VPIN11 = VREFIN + 0.1V V"10
G=
VrefIN 1.00
V''10 - V'10
0.1
3dB amplitude drop 2.0 PIN7 at 0 logic VrefIN = 2.25V
2 2.6 800 +12 100
MHz V A mV A
-12
IEA HVP% Vlogic0 Vlogic1 Ztime Top
Vref = 2.25V0%
-4
+4 0.9
% V V
1.6 Vref (Pin14) = 2.25V See Fig. 3 0C < Tcase < 80C 140 340 4
s s
Note 1: Selectable by external resistors. Note 2: Set by external Coil and Capacitor from 80 to 550KHz. Note 3: Take into account the total power dissipation.
Figure 1. Load Regulation
36 34
8V 9V 10V 11V 12V
32
30 28 26 24
7V
6V
5V
22
1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61 65 Load DC Current (mA)
OPERATIONAL AMPLIFIERS DESCRIPTION Each driver has two output stages scaled in current by a factor K = 10. In voltage mode configuration the two outputs are shorted. In charge mode configuration OUT1 drives a capacitor Cint and is closed in feedback, while OUTK drives the piezo, mirroring the current supplied to Cint, with a current multiplied by a K factor (see Fig.2). The supply voltage can be internally generated by the DC-DC converter, or external, maintaining the DC-DC converter in sleep mode (PIN3 shorted to ground), in this case the supply voltage can be 0 to V5/12+4 minimum value up to 70V in single supply or V5/12+4 to 35V symmetrical to ground. The drivers have 130dB DC gain and the Bandwidth is 500KHz. Stability is guaranteed with a minimum gain of 20dB, for a capacitive load in the range 0.4nF up to 24nF. The drivers can be supplied with HVP-HVM (dou-
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HVPVoltage
L6660
ble supply mode) or with HVP-Ground (single supply mode). In both cases they can achieve a rail-to rail output dynamic range with an average load current up to 75mA. In double supply mode the input stage has 5V/+5V common mode dynamic range, while in single supply configuration it has 1.2V up to 10V input common mode dynamic range.
Figure 2. Charge Mode Configuration (configuration example; the final application depends on user needs according with Electrical Characteristics).
Qpiezo=K*[Cint*(1+Ra/Rb)+C]*Vdac Qpiezo=Cost*Vdac Cost=k*[Cint*(1+Ra/Rb)+C] HVP 1 K
Vdac
+ Cpiezo HVM 1 K RP
Rb C
Ra Cint
D98IN970A
Input Multiplexer MULTIPLEXER is controlled by internal logic with 3 digital inputs, supplied by IntVref (2.5V), it is compatible to 3.3V and 5V logic command signals, it allows to perform the following configuration: Table 1.
AandB (PIN1) 0 0 1 1 1 1 AorB WENA (PIN4) (PIN15) 1 0 1 0 1 0 X X 1 1 (F.E.) (F.E.) INA+Status INA+ connected to AGND INA+ connected to PIN9 INA+ connected to PIN9 INA+ connected to AGND INA+ connected to PIN9 INA+ connected to PIN9 INB+Status INB+ connected to AGND INB+ connected to PIN16 INB+ connected to AGND INB+ connected to PIN16 INB+ connected to AGND INB+ connected to PIN16 Comment Both drv. inp. are disconnected from ext PIN and are connected to AGND Both drv. inp. are accesible (MUX is transparent) INA is selected INB is selected From WENA Falling Edge, changes on AorB (pin 4) will not change MUX state. From WENA Falling Edge, changes on AorB (pin 4) will not change MUX state.
F.E. = Falling Edge The MUX is at NOT inv. Inputs, and NO current flows through the MUX switches, because the driver input stage is designed with high impedance stage.
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L6660
Figure 3. Not selected driver return to Zero Output voltage. Both drivers have the same behavior. The device is in operative condition and AandB (Pin1) and WENA (Pin15) are at 1 logic condition. The external feedback programmed for a DC gain value <30V/V.
Drivers OUTPUT Voltage +20V
Deselected Driver Output Voltage
+1V 0
t
AorB (PIN4) Ztime
AorB (PIN4) Ztime Drivers OUTPUT Voltage 0 -1V t
Deselected Driver Output Voltage
-20V
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L6660
Not selected Output return to 0V Using the Multiplexer features and selecting just one driver, the second one, leaves its output voltage and "goes" to 0V (have showed in Fig. 3), in "long time" with controlled slope see table 1. Voltage reference An internal 2.5V voltage reference generator is connected to PIN13 (VrefOUT); it is based on an internal Band-Gap reference with a total precision of 3% and a current capability of 1.0mA, it is always present even in sleep mode condition. This voltage is used to supply the internal MUX logic, allowing both 3.3V or 5V logic input signals, also the internal bias current is based on this reference. The DC-DC converter reference voltage comes from PIN14 (VrefIN), so that the user can use an external voltage reference (from 2.0V up to 2.6V) or the internal one, in this case, just shorting together VrefOUT and VrefIN (PIN13 and PIN14). Voltage Shifter A voltage shifter is inserted to allow a ground symmetrical driving voltage on the piezo, starting from a positive (0V up to 5V) input signal coming from a positive supplied DAC. The DC Input-Output typical tranfer function is plotted in Fig. 4. This block works only in Double Supply mode, obviously it doesn't work if no negative supply is present. The voltage shifter output has not DC-current capability. For more details see the application note. DC-DC CONVERTER DESCRIPTION The DC-DC converter inside the chip can be supplied from 5V up to 12V and has two parts, one to supply the positive and one to supply the negative voltage. The DC-DC converter loop "measures" the HVP voltage by the EXTERNAL voltage divider and Figure 4. Shifter DC transfer function
Vosh PIN10 VIN,MAX - VrefIN
PIN21. The HVP voltage is programmed by two external resistors as shown in the block diagram, its value is: VHVP = VPIN21 (1 + Rfdb1 ) Rfdb2
The DC-DC control loop precision will be improved lower than 4% respect external reference voltage and resistor voltage divider. In Sleep Mode HVM is shorted to GND. When in single supply, HVM must be connected to GND. The topology is a standard resonant full-wave boost one: the LC oscillation is kept running all the time and a set of comparators is used to synchronize turning on and off of the power MOS in order to have zero current and zero voltage switching and furthermore controlled rectification. The step-up converter is designed to work in Linear mode, and an AC compensation network is required (RC-comp) to guarantee the stability in a wide operative range (i.e. changing coil, load, output and input voltage...). According to the ouput voltage, the current loaded into the coil is changing like a Voltage Loop-Current Controlled system, and in every pulse there is a regulated power transfer to the load. The resonant LC topology has been chosen in order to limit the voltage slew-rate across the coil within reasonable values and so, to minimize radiation problems. The negative converter is a simple charge transfer: it is supplied by the positive high voltage and it capacitively translates this positive voltage down to a negative one, obviously to limit radiation problems also the charge output has a limited slew-rate; moreover to reduce intermodulation phoenomenas the charge output is synchronized with the LC oscillations of the resonant boost. This negative voltage is (not counting drops on external rectification diodes) in tracking with the positive one and so the negative output controller is not required. If the drivers are supplied by HVP & HVM generated by external power supply the error amplifier output has to be connected to V5/12. In the external supply configuration the maximum voltage between HVP and HVM (|HVP| + |HVM|) must not exceed 70V and maximum voltage between GND and HVM must be lower than 35V.
0
VrefIN
VIN,MAX
Vin0-5 PIN11
0-VrefIN VIN,MAX =
{ V5/12 - 0.5V IF V5/12 5.5V
5.0V IF V5/12 > 5.5V
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L6660
mm DIM. MIN. A A1 A2 B C D E E1 e k L 0.25 0.50 1.51 0.25 0.10 8.35 7.60 5.02 6.10 0.65 0.30 TYP. MAX. 2.00 0.25 2.00 0.35 0.35 9.35 8.70 6.22 0.060 0.010 0.004 0.33 0.30 0.20 MIN.
inch TYP. MAX. 0.079 0.010 0.079 0.012 0.014 0.014 0.37 0.34 0.24 0.025 0 (min), 10 (max) 0.80 0.010 0.020 0.031 0.244
OUTLINE AND MECHANICAL DATA
SSO24 (SHRINK)
A2 B e A1
A K C E1
0.10mm .004 Seating Plane
L
D
24
13
E
1
12
SSO24ME
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L6660
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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